Volume 6, Issue 1, June 2020, Page: 1-6
Design of High-Performance 1-Bit Full Adder Cells Based on MOS-Type GNRFETs
Alireza Dehghan, Electronic Engineering Department, Islamic Azad University, Bandarabbas, Iran
Received: Aug. 12, 2020;       Accepted: Aug. 26, 2020;       Published: Sep. 7, 2020
DOI: 10.11648/j.ijecec.20200601.11      View  78      Downloads  28
In deep sub-micron technologies, conventional silicon-based transistors are faced main several problems related to the short-channel effects such as power dissipation, subthreshold leakage, and drain-induced barrier lowering (DIBL). Graphene nano-ribbon field-effect transistors (GNRFETs) have become a potential contender as a substitute for traditional silicon-based transistors in next generation nano-electronic devices. They exhibit fantastic properties such as high charge carrier mobility, mean free path of electrons, faster switching, and high ION/IOFF ratio. In order to prove the competences and superiority of these types of transistors, various circuits like full adder (FA) cells, which are the main building block of computational systems must be simulated and studied. This paper presents redesigning various 1-bit FA cells such as Complementary Metal-Oxide-Semiconductor (CMOS), Complementary Pass-Transistor Logic (CPL), Transmission-Gate (TG), Hybrid CMOS (HCMOS), and Transmission Function Adder (TFA) using MOS-GNRFET devices in 16nm technology node. Different HSPICE simulations are performed to obtain propagation delay, average power consumption, power-delay-product (PDP), and energy-delay-product (EDP) of FA cells and are compared with 16nm CMOS predictive technology model (PTM) at different supply voltages. The obtained results indicate that MOS-GNRFET based 1-bit FA cells have better performance than that of Si-CMOS one. The MOS-GNRFET based FA cells improve propagation delay and EDP at least 31.195% and 4.372%, respectively.
Full Adder, Graphene Nanoribbon Field-Effect Transistor (GNRFET), High-Performance, Metal-Oxide-Semiconductor (MOS)
To cite this article
Alireza Dehghan, Design of High-Performance 1-Bit Full Adder Cells Based on MOS-Type GNRFETs, International Journal of Electrical Components and Energy Conversion. Vol. 6, No. 1, 2020, pp. 1-6. doi: 10.11648/j.ijecec.20200601.11
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F. Schwierz, "Graphene transistors", Nature nanotechnology, vol. 5, no. 7, p. 487, 2010, http://doi.org/10.1038/nnano.2010.89.
Y. Banadaki, K. Mohsin, and A. Srivastava, "A graphene field effect transistor for high temperature sensing applications", Proc. SPICE (Smart Structure/NDE: Nano-, Bio-, and Info-Tech Sensors and Systems: SSNO6), vol. 9060, pp. 90600F-1-90600F-7, 2014, https://doi.org/10.1117/12.2044611.
K. Tanaka and S. Iijima (eds), Carbon nanotubes and graphene, 2nd edition, Newnes, 2014, https://doi.org/10.1016/C2011-0-07380-5.
J.-S. Moon and D. K. Gaskill, "Graphene: Its fundamentals to future applications", IEEE Transactions on Microwave Theory and Techniques, vol. 59, pp. 2702-2708, 2011, http://doi.org/10.1109/TMTT.2011.2164617.
M. Gholipour, Y.-Y. Chen, A. Sangai, N. Masoumi, and D. Chen, "Analytical SPICE-compatible model of Schottky-barrier-type GNRFETs with performance analysis", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 24, no. 2, pp. 650-663, 2016, https://doi.org/10.1109/TVLSI.2015.2406734.
M. Gholipour, Y.-Y. Chen, A. Sangai, and D. Chen, "Highly accurate SPICE-compatible modeling for single-and double-gate GNRFETs with studies on technology scaling", in Proceedings of the conference on Design, Automation & Test in Europe, p. p 1-6, 2014, https://doi.org/10.7873/DATE.2014.133.
S. Joshi and U. Albalawi, "Statistical Process Variation Analysis of Schottky-Barrier type GNRFET for RF Application", in 2017 International Conference on Current Trends in Computer, Electrical, Electronics and Communication (CTCEEC), pp. 1-6, 2017, https://doi.org/10.1109/CTCEEC.2017.8455156.
H. C. Chin, C. S. Lim, and M. L. P. Tan, "Design and performance analysis of 1-bit FinFET full adder cells for subthreshold region at 16 nm process technology", Journal of Nanomaterials, vol. 16, no. 1, p. 175, 2015, https://doi.org/10.1155/2015/726175.
A. M. Shams, T. K. Darwish, and M. A. Bayoumi, "Performance analysis of low-power 1-bit CMOS full adder cells", IEEE transactions on very large scale integration (VLSI) systems, vol. 10, no. 1, pp. 20-29, 2002, http://doi.org/10.1109/92.988727.
Y.-Y. Chen, A. Rogachev, A. Sangai, G. Iannaccone, G. Fiori, and D. Chen, "A SPICE-compatible model of graphene nano-ribbon field-effect transistors enabling circuit-level delay and power analysis under process variation", in 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 1789-1794, 2013, https://doi.org/10.7873/DATE.2013.359.
Y.-W. Son, M. L. Cohen, and S. G. Louie, "Energy gaps in graphene nanoribbons", Physical review letters, vol. 97, no. 21, p. 216803, Nov. 2006, https://doi.org/10.1103/PhysRevLett.97.216803.
Y.-Y. Chen, A. Sangai, A. Rogachev, M. Gholipour, G. Iannaccone, G. Fiori, and D. Chen, "A SPICE-compatible model of MOS-type graphene nano-ribbon field-effect transistors enabling gate-and circuit-level delay and power analysis under process variation", IEEE Transactions on Nanotechnology, vol. 14, no. 6, pp. 1068-1082, 2015, https://doi.org/0.1109/TNANO.2015.2469647.
E. Abbasian and M. Gholipour, "A variation-aware design for storage cells using Schottky-barrier-type GNRFETs", J Comput Electron, vol. 19, pp. 987–1001, 12 june 2020, https://doi.org/10.1007/s10825-020-01529-y.
S. Joshi, S. P. Mohanty, E. Kougianos, and V. P. Yanambaka, "Graphene nanoribbon field effect transistor based ultra-low energy SRAM design", International Symposium on Nano-electronic and information System (iNIS), pp. 76-79, Dec. 2016, http://doi.org/10.1109/iNIS.2016.028.
M. Hasan, M. J. Hossein, M. Hossain, H. U. Zaman, and S. Islam, "Design of a Scalable Low-Power 1-bit Hybrid Full Adder for Fast Computation", IEEE Transactions on Circuits and Systems II: Express Briefs, 2019, http://doi.org/10.1109/TCSII.2019.2940558.
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